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| NB6L611 2.5V / 3.3V 1:2 Differential LVPECL Clock / Data Fanout Buffer Multi-Level Inputs with Internal Termination Description http://onsemi.com MARKING DIAGRAM* 1 QFN-16 MN SUFFIX CASE 485G 16 NB6L 611 ALYWG G The NB6L611 is a differential 1:2 fanout buffer. The differential inputs incorporate internal 50 W termination resistors that are accessed through the VTD pins and will accept LVPECL, CML, LVDS, LVCMOS or LVTTL logic levels. The VREFAC pin is an internally generated voltage supply available to this device only. VREFAC is used as a reference voltage for single-ended PECL or NECL inputs. For all single-ended input conditions, the unused complementary differential input is connected to VREFAC as a switching reference voltage. VREFAC may also rebias capacitor-coupled inputs. When used, decouple VREFAC with a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VREFAC output should be left open. The device is housed in a small 3x3 mm 16 pin QFN package. The NB6L611 is a member of the ECLinPS MAXTM family of high performance clock products. Features A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb-Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. Q0 VTD D D VTD Q0 Q1 Q1 * * * * * * * * * * * * Maximum Input Clock Frequency > 4.0 GHz, Typical 280 ps Typical Propagation Delay 100 ps Typical Rise and Fall Times 0.5 ps maximum RMS Clock Jitter Differential LVPECL Outputs, 780 mV Amplitude, typical LVPECL Operating Range: VCC = 2.375 V to 3.63 V with VEE = 0 V NECL Operating Range: VCC = 0 V with VEE = -2.375 V to -3.63 V Internal Input Termination Resistors, 50 W VREFAC Reference Output Voltage Functionally Compatible with Existing 2.5 V / 3.3 V LVEL, LVEP, EP, and SG Devices -40C to +85C Ambient Operating Temperature These are Pb-Free Devices Figure 1. Simplified Logic Diagram ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet. (c) Semiconductor Components Industries, LLC, 2006 December, 2006 - Rev. 0 1 Publication Order Number: NB6L611/D NB6L611 VCC 16 VTD D D VTD 1 2 NB6L611 3 4 5 6 7 8 VCC 10 9 Q1 Q1 NC 15 VEE 14 VCC 13 12 11 Q0 Q0 Exposed Pad (EP) VCC VREFAC VEE Figure 2. Pin Configuration (Top View) Table 1. PIN DESCRIPTION Pin 1 2 Name VTD D I/O - ECL, CML, LVCMOS, LVDS, LVTTL Input ECL, CML, LVCMOS, LVDS, LVTTL Input - - Internal 50 W Termination Pin for D input. Noninverted Differential Input. Note1. Internal 50 W Resistor to Termination Pin, VTD. Description 3 D Inverted Differential Input. Note 1. Internal 50 W Resistor to Termination Pin, VTD. 4 5 6 7 8 9 10 11 12 13 14 15 16 - VTD VCC VREFAC VEE VCC Q1 Q1 Q0 Q0 VCC VEE NC VCC EP Internal 50 W Termination Pin for D input. Positive Supply Voltage Output Reference Voltage for direct or capacitor coupled inputs - - LVPECL Output LVPECL Output LVPECL Output LVPECL Output - - - - - Negative Supply Voltage Positive Supply Voltage Inverted Differential Output. Typically Terminated with 50 W Resistor to VCC - 2.0 V. Noninverted Differential Output. Typically Terminated with 50 W Resistor to VCC - 2.0 V. Inverted Differential Output. Typically Terminated with 50 W Resistor to VCC - 2.0 V. Noninverted Differential Output. Typically Terminated with 50 W Resistor to VCC - 2.0 V. Positive Supply Voltage Negative Supply Voltage No Connect Positive Supply Voltage The Exposed Pad (EP) on the QFN-16 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heat-sinking conduit. The pad is not electrically connected to the die, but is recommended to be electrically and thermally connected to VEE on the PC board. 1. In the differential configuration when the input termination pins (VTD, VTD) are connected to a common termination voltage or left open, and if no signal is applied on D/D input, then, the device will be susceptible to self-oscillation. 2. All VCC and VEE pins must be externally connected to a power supply for proper operation. http://onsemi.com 2 NB6L611 Table 2. ATTRIBUTES Characteristics ESD Protection Moisture Sensitivity Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test For additional information, see Application Note AND8003/D. Human Body Model Machine Model 16-QFN Oxygen Index: 28 to 34 Value > 2 kV > 200V Level 1 UL 94 V-0 @ 0.125 in Table 3. MAXIMUM RATINGS Symbol VCC VEE VIO VINPP IIN IOUT IVREFAC TA Tstg qJA qJC Tsol Parameter Positive Power Supply Negative Power Supply Positive Input/Output Voltage Negative Input/Output Voltage Differential Input Voltage |D - D| Input Current Through RT (50 W Resistor) Output Current (LVPECL Output) VREFAC Sink/Source Current Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) (Note 3) Thermal Resistance (Junction-to-Case) Wave Solder Pb-Free 0 lfpm 500 lfpm (Note 3) QFN-16 QFN-16 QFN-16 16 QFN Static Surge Continuous Surge Condition 1 VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V -0.5 v VIo v VCC + 0.5 +0.5 w VIo w VEE - 0.5 Condition 2 Rating 4.0 -4.0 4.0 -4.0 2.8 45 80 50 100 $2.0 -40 to +85 -65 to +150 42 35 4 265 Unit V V V V V mA mA mA mA mA C C C/W C/W C/W C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 3. JEDEC standard multilayer board - 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad. http://onsemi.com 3 NB6L611 Table 4. DC CHARACTERISTICS, Multi-Level Inputs VCC = 2.375 V to 3.63 V, VEE = 0 V, or VCC = 0 V, VEE = -2.375 V to -3.63 V, TA = -40C to +85C Symbol POWER SUPPLY CURRENT ICC VOH Power Supply Current (Inputs and Outputs Open) 30 45 60 mA Characteristic Min Typ Max Unit LVPECL OUTPUTS (Notes 4 and 5) Output HIGH Voltage VCC = 3.3 V VCC = 2.5 V VCC = 3.3V VCC = 2.5V VCC - 1075 2225 1425 VCC - 1875 1475 675 VCC - 950 2350 1550 VCC - 1725 1575 775 VCC - 825 2475 1675 VCC - 1625 1675 875 mV VOL Output LOW Voltage mV DIFFERENTIAL INPUT DRIVEN SINGLE-ENDED (see Figures 4 and 5) (Note 6) Vth VIH VIL VISE VREFAC VREFAC VIHD VILD VID VCMR IIH IIL RTIN Output Reference Voltage VCC - 1.525 VEE + 1200 VEE VEE + 150 VEE + 1125 -10 -50 VCC - 1.425 VCC - 1.325 VCC VCC - 150 2800 VCC - 75 50 10 mV DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (see Figures 6, 7 and 8) (Note 8) Differential Input HIGH Voltage Differential Input LOW Voltage Differential Input Voltage (VIHD - VILD) Input Common Mode Range (Differential Configuration) (Note9) Input HIGH Current D/D, (VTD/VTD Open) Input LOW Current D/D, (VTD/VTD Open) mV mV mV mV mA mA Input Threshold Reference Voltage Range (Note 7) Single-ended Input HIGH Voltage Single-ended Input LOW Voltage Single-ended Input Voltage Amplitude (VIH - VIL) VEE + 1125 Vth + 75 VEE 150 VCC - 75 VCC Vth - 75 2800 mV mV mV mV TERMINATION RESISTORS Internal Input Termination Resistor (Measured from D to VTD) 40 50 60 W NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. LVPECL outputs loaded with 50 W to VCC - 2.0 V for proper operation. 5. Input and output parameters vary 1:1 with VCC. 6. Vth, VIH, VIL,, and VISE parameters must be complied with simultaneously. 7. Vth is applied to the complementary input when operating in single-ended mode. 8. VIHD, VILD, VID and VCMR parameters must be complied with simultaneously. 9. VCMR minimum varies 1:1 with VEE, VCMR maximum varies 1:1 with VCC. The VCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 4 NB6L611 Table 5. AC CHARACTERISTICS VCC = 2.375 V to 3.63 V, VEE = 0 V, or VCC = 0 V, VEE = -2.375 V to -3.63 V, Symbol VOUTPP Characteristic Output Voltage Amplitude (@ VINPP) (Note 14) (See Figure 9) Propagation Delay Duty Cycle Skew (Note 11) Within Device Skew Device to Device Skew (Note 12) Output Clock Duty Cycle (Reference Duty Cycle = 50%) RMS Random Clock Jitter (Note 13) Input Voltage Swing/Sensitivity (Differential Configuration) (Note 14) Output Rise/Fall Times @ 0.5 GHz (20% - 80%) Q, Q fin 4.0 GHz fin 4.0 GHz 150 100 40 fin 2.0 GHz 2.0 GHz fin 3.0 GHz 3.0 GHz fin 4.0 GHz D to Q Min 520 320 170 225 Typ 600 500 400 280 3 50 0.2 375 15 15 80 60 0.5 2800 170 Max Unit mV TA = -40C to +85C; (Note 10) tPD tSKEW ps ps tDC tJITTER VINPP tr,tf ps ps mV ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 10. Measured by forcing VINPP (MIN) from a 50% duty cycle clock source. All loading with an external RL = 50 W to VCC - 2.0 V. Input edge rates 40 ps (20% - 80%). 11. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw- and Tpw+ @ 0.5GHz. 12. Device to device skew is measured between outputs under identical transition @ 0.5 GHz. 13. Additive RMS jitter with 50% duty cycle clock signal. 14. Input and output voltage swing is a single-ended measurement operating in differential mode. http://onsemi.com 5 NB6L611 VTD 50 W D VCC RC RC I D 50 W VTD Figure 3. Input Structure VIH Vth VIL D VCC Vthmax VIHmax VILmax VIH Vth VIL VIHmin VILmin Vth D Vth Vthmin VEE Figure 4. Differential Input Driven Single-Ended Figure 5. Vth Diagram D D D D VID = |VIHD(D) - VILD(D)| VIHD VILD Figure 6. Differential Inputs Driven Differentially Figure 7. Differential Inputs Driven Differentially VCC VIHD(MAX) VILD(MAX) D D VINPP = VIH(D) - VIL(D) VCMR VIHD VID = VIHD - VILD VILD VIHD(MIN) Q Q tPD VOUTPP = VOH(Q) - VOL(Q) tPD GND VILD(MIN) Figure 8. VCMR Diagram Figure 9. AC Reference Measurement http://onsemi.com 6 NB6L611 VCC VCC VCC VCC ZO = 50 W LVPECL Driver VT = VCC - 2 V ZO = 50 W NB6L611 D 50 W 50 W D LVDS Driver ZO = 50 W VT = Open ZO = 50 W NB6L611 D 50 W 50 W D VEE VEE VEE VEE Figure 10. LVPECL Interface Figure 11. LVDS Interface VCC VCC ZO = 50 W CML Driver VT = VCC ZO = 50 W NB6L611 D 50 W 50 W D VEE VEE Figure 12. Standard 50 W Load CML Interface VCC VCC VCC VCC ZO = 50 W Differential Driver VT = VREFAC* ZO = 50 W NB6L611 D 50 W 50 W D Single-Ended Driver ZO = 50 W VT = VREFAC* NB6L611 D 50 W 50 W D (Open) VEE Figure 13. Capacitor-Coupled Differential Interface (VT Connected to VREFAC) VEE VEE Figure 14. Capacitor-Coupled Single-Ended Interface (VT Connected to VREFAC) VEE *VREFAC bypassed to ground with a 0.01 mF capacitor http://onsemi.com 7 NB6L611 VOUTPP OUTPUT VOLTAGE AMPLITUDE (mV) (TYPICAL) 800 700 600 500 400 300 200 100 0 0 1 2 3 4 fout, CLOCK OUTPUT FREQUENCY (GHz) Figure 15. Output Voltage Amplitude (VOUTPP) versus Output Frequency at Ambient Temperature (Typical) Q Driver Device Q Zo = 50 W D Receiver Device Zo = 50 W 50 W 50 W D VTT VTT = VCC - 2.0 V Figure 16. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D - Termination of ECL Logic Devices.) ORDERING INFORMATION Device NB6L611MNG NB6L611MNR2G Package QFN-16 (Pb-free) QFN-16 (Pb-free) Shipping 123 Units / Rail 3000 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 8 NB6L611 PACKAGE DIMENSIONS 16 PIN QFN MN SUFFIX CASE 485G-01 ISSUE C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. Lmax CONDITION CAN NOT VIOLATE 0.2 MM MINIMUM SPACING BETWEEN LEAD TIP AND FLAG DIM A A1 A3 b D D2 E E2 e K L MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 3.00 BSC 1.65 1.85 3.00 BSC 1.65 1.85 0.50 BSC 0.18 TYP 0.30 0.50 D A B PIN 1 LOCATION 0.15 C 0.15 C 0.10 C 16 X 0.08 C 16X L NOTE 5 4 16X K 1 16 16X 13 b BOTTOM VIEW 0.10 C A B 0.05 C NOTE 3 ECLinPS MAX is a trademark of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800-282-9855 Toll Free Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Phone: 81-3-5773-3850 Email: orderlit@onsemi.com ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. CC CC TOP VIEW (A3) SIDE VIEW D2 5 E A A1 SEATING PLANE C SOLDERING FOOTPRINT* e 8 EXPOSED PAD 9 0.575 0.022 E2 e 3.25 0.128 0.30 0.012 EXPOSED PAD 12 3.25 0.128 1.50 0.059 0.50 0.02 0.30 0.012 SCALE 10:1 mm inches *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 9 NB6L611/D |
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